This invention relates generally to MIS (Metal-Insulator-Semiconductor) type integrated circuit devices, and more particularly to an improved MIS type integrated circuit device in which a semiconductor substrate is supplied with a bias voltage which increases the threshhold voltage of MIS type transistors included in the integrated circuit (hereinbelow referred to as a back-gate bias).
Since positive charges tend to be accumulated in a silicon oxide film used as a gate insulating film in MIS type integrated circuit devices, the semiconductor surface just beneath the gate insulating film of an N-channel MIS type transistor is easily converted to N type. Therefore, an N-channel MIS type transistor inevitably becomes the depletion type, even if the gate voltage is maintained at zero volts. MIS type transistors of the enhancement type needed for digital IC applications can be obtained by the application of a back-gate bias to the semiconductor substrate. With the back-gate bias applied to the semiconductor substrate in an integrated circuit device incorporating MIS type transistors, both the threshhold voltage (hereinafter abbreviated as VT1) of the MIS type transistor in the circuit and the threshhold voltage (hereinafter abbreviated as VT2) of a parasitic transistor to be formed between adjacent diffused regions in the semiconductor substrate can be made higher than that which can be obtained with the semiconductor substrate grounded, thereby widening the operating range of the circuit.
Suppose now that such an MIS type integrated circuit device incorporating N-channel MIS type transistors is operated with the back-gate bias applied to the P type semiconductor substrate and used with the substrate in an unbiased condition as a result of a delay in the application of the back-gate bias voltage at the moment the power supply is applied to the circuit of the device. This causes positive charges to leak from P-N junctions and channel portions in the circuit to the substrate. Since the charges flow toward grounded N type regions through the P-N junctions formed between the substrate and the grounded N type regions, the polarity of the potential of the substrate will become that of the circuit power supply potential for the presence of the voltage vs. current characteristics of the P-N junctions to reach a value of the order of for example, +0.5 volts. Because of this phenomenon, VT.sub.2 is lowered further than expected in a case in which the substrate and the grounded region are equipotential, thus resulting in degradation in electrical isolation between transistors. Consequently, current flows in portions of the integrated circuit which should be essentially isolated electrically, and the circuit current abnormally increases, which may affect the life span of the integrated circuit.
Power supply devices conventionally used are so contrived that the back-gate bias can be applied to the substrate prior to the application of a voltage to the circuit. Such devices are invariably expensive as compared to ordinary devices. The same problem mentioned above has also arisen in cases in which an MIS type integrated circuit device is used under a condition of power supply application with the substrate kept released from the back-gate bias.
It is consequently an object of this invention to provide an MIS type integrated circuit device, in which the substrate potential does not increase toward the potential of the circuit power supply when the semiconductor substrate is in an electrically floating state and the possibility of an excessive increase in current flowing in the circuit is eliminated.